1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com AN179 application note interfacing a color lcd to the ep72xx note: cirrus logic assumes no responsibility for the attached information which is provided as is without warranty of any kind (expressed or implied). jun 00 AN179rev1
AN179 2 AN179rev1 table of contents 1. introduction .............................................................................................................. ......... 3 2. ep72xx lcd controller description ......................................................................... 3 3. how gray-scaling works .............................................................................................. 4 4. color support ............................................................................................................. ...... 4 5. the lcd display interface port .................................................................................. 6 6. example color display interface ............................................................................. 6 7. known compatible lcd display modules ................................................................ 7 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
AN179 AN179rev1 3 1. introduction as the world of pdas and other hand-held devices evolves, more and more of these products need the support of color displays. today, the use of color displays constitutes only a small market share. however, the desire for color support is growing dramatically. this application note is created to support this trend. this application note describes how the lcd controller integrated into the cirrus logic ep72xx embedded processor can be used to drive a color lcd display. this application note will first describe in detail how the ep72xxs lcd controller can be used to support color displays. (see section 2). next, it will provide an example of an application using a sharp lm057qctt03 ? vga color lcd module. finally, it will provide a list of other color lcd modules that are known to be compatible with lcd controller in the ep72xx. 2. ep72xx lcd controller description the lcd controller provides all the necessary control signals to interface directly to a single- panel, multiplexed lcd. the ep72xx uses the universal memory architecture (uma) for storing the video frame buffer. it shares the main memory bus with the core processor (i.e., the arm720t). the total frame buffer size can be programmed up to 128 kbytes. the panel size is programmable and can basically support any panel size available, including the support for full vga sizes. any width (line length) from 32 to 1024 in 16-pixel increments can be programmed. the total number of lines (rows) supported is solely determined by the total frame buffer size programmed, divided by the panel width and color depth programmed. the controller can also be programmed to provide 1-, 2-, or 4-bits-per-pixel color depth. the use of these bits is up to the application. they can be used to support a monochrome, gray-scale, or color display. as an example: if a 1/2 vga display is used, and 4 bpp is desired, the video buffer size field in the lcd control register (lcdcon) will have to be programmed to equal 640 x 240 x 4 = 614,400 bits = 76,800 bytes. the line length field in the register will have to be programmed to equal 640, and the color depth field will have to be programmed to equal 4. these three settings will result in the support for the 240 lines. to support the various possible colors and gray- scale levels, the lcd controller has two 32-bit palette registers. these palette registers are broken down into eight addressable nibbles each. this makes a total of sixteen nibbles. the nibbles are addressed by the data in the frame buffer. when the lcd controller is configured to support 4 bpp, each four bits of data in the frame buffer is used to represent one pixel. each of these nibbles addresses one of the sixteen nibbles in the two palette registers. for example, if a nibble in the frame buffer contained the decimal value of ten, it would point to the tenth nibble in the two palette registers. this addressing scheme is used to map the data value in the frame buffer to the actual gray-scale level that will be supplied to the display interface. when 4 bpp mode is configured, all sixteen nibbles in the palettes registers are used for the mapping. this of course, is due to the fact that four bits can provide sixteen different values. when 2 bpp mode is configured, only the lowest addressable four nibbles are used. when in 1 bpp mode, only the lowest two nibbles are used. each palette register nibble can be programmed with a value from 0 to 15. these sixteen different values correspond to 16 different color depth levels. when the value programmed into each nibble matches its nibble address, the frame buffer data corresponds exactly with the gray-scale levels. this is the usual approach.
AN179 4 AN179rev1 when the value programmed into any of the nibbles does not match its nibble address, then interesting patterns can be generated on the display. for example, if it is desirable to toggle the displays image between normal and reverse video, this can easily be achieved by simply inverting the values in the nibbles of the palette registers. this is much quicker and easier than having to invert all of the data in the frame buffer. the lcd controller also contains a nine-word deep fifo. it is used as an intermediate storage buffer for the frame data. an integrated dma controller is used to fetch display data from the frame buffer memory, and refill the fifo. thus, once the lcd controller is configured and the frame buffer data is stored, the ep72xx can continue executing other tasks, and without having to service the lcd controller. note: this dma controller is dedicated to servicing the lcd controller. it cannot be used for any other purpose. 3. how gray-scaling works when a product has a lcd display that is providing different gray-scale levels, it isnt actually using a display that can be programmed to drive each pixel with a different level of intensity. the displays actually only have the ability to either fully turn on each pixel or turn it off. one of the poor characteristics of lcd displays in general is their response time. the response time can be defined as the amount of time it takes for a pixel to change from being turned on to off, and vice versa. typical response times are in the hundreds of milliseconds. the technique used for gray scaling takes advantage of this weakness. a modulating technique is used to drive each pixel. this technique drives each pixel a percentage of the time over a fixed time period. within the lcd controller is a sixteen-cycle counter. it is used to create a sixteen-cycle period. when the lcd controller needs to drive a pixel, it reads the value of the palette nibble pointed to by the frame buffer data. the value is used to determine how often within a sixteen-cycle period, the pixel needs to be turned on. for example, if the value is 4, then the pixel would be turned on once every four clock cycles. this equates to 4/16 of the available sixteen-cycle period. by doing this, the naked eye thinks the pixel was actually being driven at ? the maximum brightness level. in actuality, the nibble value does not correlate one-to-one with the number of times in the period that the pixel is turned on. this is due to non- linear characteristics of the response time. the ep72xx data sheets include a table that contains the actual gray-scale value mappings. the table is called the gray-scale value to color mapping. it can be found in the palette register section. 4. color support when used with a so-called monochrome lcd display, it provides support for up to 15 different gray-scale levels. note: fifteen is the correct number, not 16. this is due to the fact that the middle two gray-scale levels are identical in contrast, and thus only provide one level instead of two. color displays have three sub-pixels per pixel. each pixel is made-up of three sub-color pixels (red, green, and blue). the same technique described above for gray-scaling is applied to color displays. hence, each sub-color pixel can be modulated to provide the perceived affect of supporting 15 different shades of its color. therefore, one pixel can be driven with one of fifteen possible shades of red, green, and blue. the lcd controller can support up to 15 x 15 x 15 = 3,375 different colors. this is based upon the assumption that the lcd controller has been programmed to provide 4 bpp. now each nibble in the frame buffer represents one of the sub-pixels in the display. when programmed to provide 2 bpp, 2 2 x 2 2 x 2 2 = 64 different colors can be supported.
AN179 AN179rev1 5 when programmed to provide 1 bpp, 2 1 x 2 1 x 2 1 = 8 different colors can be supported.o support a ? vga color display, the actual number of pixels triples due to the three sub-pixels. this equates to 320 (x3) x 240 = 230,400 pixels. if programmed to 4 bpp to support the maximum number of colors, the frame buffer size becomes 230,400 x 4 = 921,600 bits, or 115,200 bytes in size. this falls within the maximum size constraints of the frame buffer (i.e., 128 kbytes) mentioned above. another characteristic of displays is their refresh rate. the refresh rate is a number that states how frequently the entire frame of data can be rewritten to the display. if the data is written too slowly, the displays response time will affect the quality of its appearance. too fast, and the displays response time will not be able to keep up with the changing pixel drive states. most displays today recommend rates around 70 C 80 hz. the lcd controller has a fixed-clock source, which is used to generate the frequency that the pixels are written to the display. when the ep72xxs pll is used to create its clocks, the lcd controller is provided with a 36.864 mhz clock. when the ep72xx is supplied a 13 mhz external clock, the lcd controller is supplied with a 13 mhz clock. these fixed clock sources place limits on the maximum rate that the pixels can be written to the display. thus there is a limit on the maximum refresh rate. the ep72xx device has a field in the lcd control register (lcdcon) called the pixel prescale. the pixel prescale field is a 6-bit field that sets the pixel rate prescale. when the ep72xx pll is used to create its clocks, the pixel rate is derived from equation 1. the pixel prescale value can be expressed in terms of the lcd size by equation 2. the value should be rounded down to the nearest whole number and zero is illegal and will result in no pixel clock. for a ? vga color display, the maximum refresh rate can be calculated by using the equations below. rearranging equation 2 to solve for the maximum refresh rate results in equation 3. since, the minimum pixel prescale value is 1, we use this value in equation 3 to calculate the maximum refresh rate, as shown in equation 4. the lcd controller can provide a maximum refresh rate of 80 hz, for a ? vga color lcd display. this is perfect for most displays. if color is desired, the maximum recommended display size is a ? vga color lcd display. this is solely due to their minimum required refresh rate. if a ? vga color display is chosen, the lcd controller can only provide a maximum refresh rate of 40 hz (per equation 3). this is too slow for most displays. if a monochrome display is chosen, the lcd controller can support a full vga display pixel rate (mhz) = 36.864/(pixel prescale C1) equation 1 pixel prescale = (36864000/(refresh rate x total pixels in display)) C 1 equation 2 refresh rate = 36864000/ (total pixels in display) x (pixel prescale + 1) equation 3 maximum refresh rate = 36864000/((320 (x3) x 240) x (1 + 1)) = 80 hz equation 4
AN179 6 AN179rev1 with a refresh rate of 60 hz; along with support for up to 2 bpp, or 4 gray-scale levels. note: the refresh rate is completely independent of the number of bits per pixel selected. 5. the lcd display interface port the lcd display interface port built into the ep72xx device, contains the following signals: dd[0:3] frm cl1 cl2 m dd[0:3] are the four data lines. when the lcd controller writes out this port, it presents four pixels at a time using these lines. each data line is either high or low. thus each pixel value is either high or low. frm is the frame sync signal. it toggles high after all of the pixel data for a frame has been completely written out the interface. it is used by the display to force it to reset its line (row) counter back to zero. thus, the display will start driving the next nibble of data to the first line of the display. cl1 is the line strobe signal. it toggles high after all of the pixel data for a line has been written out the interface. cl2 is the pixel data clock. it is used by the display to clock in each nibble of pixel data. its period is ? the actual pixel rate. when cl1 toggles, cl2 stays low. thus, cl2 low time is doubled when cl1 toggles at the end of each line. m is the ac bias signal. this signal is used by the display to tell it when the drive voltage to the display should be reversed. if used, it becomes active high for a programmed quantity of cl2 cycles during each cl1 cycle. this is done periodically to minimize any dc voltage bias that may build-up across the display. dc voltage build- up is undesirable, since it can damage the display. the value for m is based upon the exact display being used. therefore, the value must be obtained from the displays datasheet. 6. example color display interface the schematic diagram of 1 depicts one example solution of interfacing the ep72xx lcd controller to a sharp lm057qctt03 ? vga color lcd module. this display has an 8-bit data interface. the sole purpose of this logic is to convert the 4-bit interface into an 8-bit. it creates an 8-bit interface out of two 4-bit nibbles. this logic has no affect on the programming of the lcd controller registers. the lcd controller will provide the same refresh rate and pixel color depth. the left side of the schematic has all the input signals from the lcd controller. the right side has all the output signals that connect directly to the display. since the data provided to the display is made up of two sets of data that is output from the ep72xx, the clock supporting this 8-bit data word, must be half the rate as the original. this means that cl2 from the ep72xx must be halved. this is accomplished by use of the d flip-flop configured to toggle its output every time its clock toggles high. by using ep72xx_cl2 as the input clock, the output toggles at ? the clock rate, and thus becomes the desired lcd_cl2. ep72xx_cl1 is routed directly to the display. it is also used to reset the d flip-flop so that the signal lcd_cl2 starts off in the low state. the 174 register is used to store the lower half of the 8-bit data word. when the upper nibble is available, both nibbles are provided to the display together.
AN179 AN179rev1 7 7. known compatible lcd display modules table 1 gives a list of lcd display modules that are known to be compatible with lcd controller integrated into the ep72xx device. note: the list in table 1 is based solely upon work that was done to create this application note. many other display modules are compatible as well, including display sizes up to full vga. however, if a full vga display module is desired, the color depth will be restricted due to the limits on the maximum frame buffer size and the maximum pixel rate (i.e., refresh rate) supported. sharp lm057qc1t01 8-bit, 6.1", 320 x 240, color display, no touchscreen sharp lm057qctt03 8-bit, 6.1", 320 x 240, color transmissive, cctf backlight, touchscreen sharp lm038qc1r10 8-bit, 3.8", 320 x 240, color reflective, no backlight, no touchscreen sharp lm038qc1s10 8-bit, 3.8", 320 x 240, color tranflective, ccft backlight, no touchscreen q3/00 sharp lm038qc1ts10 8-bit, 3.8", 320 x 240, color transflective, ccft backlight, touchscreen q3/00 sharp lm038qb1r10 4-bit, 3.8", 320 x 240, monochrome reflective, no backlight, no touchscreen sharp lm038qb1s10 4-bit, 3.8", 320 x 240, monochrome transflective, el backlight, no touchscreen sharp lm038qbts10 4-bit, 3.8", 320 x 240, monochrome transflective, el backlight, touchscreen alps lrhdd1014a 4-bit, 6.8", 640 x 240, monochrome display, touchscreen alps lrhdd1013a 4-bit, 6.8", 640 x 240, monochrome display, touchscreen alps lrh7u504xa 4-bit, 2.9", 320 x 240, monochrome display, touchscreen alps lfh8p402xa 4-bit, 2.8", 320 x 240, monochrome display, touchscreen table 1. compatible lcd display modules
AN179 8 AN179rev1 ep72xx_frm lcd_cl1 lcd_d5 lcd_en ep72xx_cl1 ep72xx_m ep72xx_dd[1] lcd_d7 lcd_d4 lcd_m ep72xx_lcd_en vdd lcd_d6 ep72xx_dd[0] lcd_d1 lcd_d0 lcd_cl2 ep72xx_dd[3] vdd u1a 74lcx04 1 2 lcd_d2 lcd_frm ep72xx_cl2 lcd_d3 u2a 74lcx04 1 2 r c1 1d u4 74lcx174 1 9 3 4 6 11 13 14 15 12 10 7 5 2 u8a 74lcx74 2 3 5 6 4 1 d clk q q pr cl ep72xx_dd[2] figure 1. ep72xx interface to 8-bit color display
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